M62021L Datasheet, PDF (8/14 Pages) Mitsubishi Electric Semiconductor – SYSTEM RESET IC WITH SWITCH FOR MEMORY BACK-UP

M62021L/P/FP
Timing Chart
t_pd
5V
V_IN
0V
V_OUT
t_pd
V_SH
∆V_S
V_SL
V1
V2
V3
V4
V5
CS
RES
RES
V2
V4
V5
V_OL(CS)
5V
V_IN(V_SL)
V_OL(RES)
V_OH(RES)
V_IN(V_SL)
V1 = V_IN – V_DROP
V2 = V_IN – Q4V_EB(Di)
V3 = V_IN(V_SL) – V_DROP
V_OL(RES)
V4 = V_IN(V_SL) – Q4V_EB(Di)
V5 = V_BAT – V_F
Figure 6 Timing Chart
Input
Voltage
Output
Pin
VOUT
RES
RES
CS
In Normal Operation
Input voltage: 5V
With Q4 set to ON,
a voltage (VIN – VDROP)
is output
The output level is VOL
(RES) with a logic low
The output level is VOH
(RES) with a logic low
The output level is VOL
(CS) with a logic low
In Failure (Instantaneous
Drop)
Input voltage: 5V→4V
Each output varies if the input
voltage drops to VSL or under
Q4 is turned OFF. A voltage
(VIN – Q4VEB(Di)) is output by
the diode between E and B of
Q4.
As the state shifts from a logic
low to logic high, the output
level becomes approximately
equal to the input voltage.
As the state shifts from a logic
high to logic low, the output
level becomes VOL (RES).
As the state shifts from a logic
low to logic high, the output
level becomes the voltage VIN –
Q4VEB(Di).
Restoration from Failure
(Instantaneous Drop)
Input voltage: 4V→5V
If the input voltage goes higher
than VSL by 100mV, each
output varies after delay
produced by the delay circuit
Q4 is turned ON after delay
and a voltage (VIN – VDROP) is
output.
A logic high is maintained, and
than shifts to a logic high.
A logic low is held, and than
shifts to a logic high.
A logic high is maintained, and
than shifts to a logic high.
In Backup State
Input voltage: 0V
Backup voltage: 3V
VBAT – VF
—
—
The output is a logic
high and the output
level is VBAT – VF
REJ03D0784-0200 Rev.2.00 Jun 15, 2007
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