M61113FP Datasheet, PDF (8/17 Pages) Hitachi Semiconductor – Semiconductor integrated circuit built-in the PLL inter-carrier method VIF/SIF dedicated to NTSC.

M61113FP
VIF Section 2
(Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. Parameter
Test
Test Input Input SW
Limits
Symbol circuit point point signal condition _{Min Typ Max} Unit
Note#
21 AFT sensitivity µ
1
TP13 Pin16, SG13
17
10 26 40
mV/
10
kHz
22 AFT High
voltage
AFTH
1
TP13 Pin16, SG14
17
4.3 4.7 5
V
10
23 AFT Low
voltage
AFTL
1
TP13 Pin16, SG15
17
0
0.3 0.7 V
10
24 AFT Mute
voltage
AFTM
1
TP13 Pin16, SG16
17
2.4 2.5 2.6 V
25 AFT Center
voltage @US
mode
VaftUS 1
TP13 Pin16, SG2
17
2.40 2.65 2.90 V
26 AFT Center
voltage @JP
mode
VaftJP 1
TP13 Pin16, SG17 SW8=2
17
2.60 2.87 3.15 V
SIF Section
(Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. Parameter
Test
Test Input Input SW
Limits
Symbol circuit point point signal condition _{Min Typ Max} Unit
Note#
27 AF output level VoAF
1
TP9 Pin7 SG18 SW7=2
400 700 1000 mVrms
28 AF output THD THDAF 1
TP9 Pin7 SG18 SW7=2
— 0.4 0.9 %
29 Audio S/N
AF S/N 1
TP9 Pin7 SG19 SW7=2
50 55 —
dB
11
SW19=2
30 Limiting
sensitivity
LIM
1
TP9 Pin7 SG20 SW7=2
SG21 ^SW19=2
—
50 55
dBuV 12
31 SIF output level SIFG
1
TP8 Pin7 SG19 SW7=2
90 96 102 dBuV
VCO Section
(Unless otherwise specified: Ta = 25°C, Vcc = 5.0 V, Ref Signal = 3.579545 MHz, Vi = 100 mVpp, SW = 1)
No. Parameter
Test
Test Input Input SW
Limits
Symbol circuit point point signal condition _{Min Typ Max} Unit
Note#
32 VIF VCO
freerun @US
mode
FvcofUS 1
TP13 —
—
SW10=2
-500 0
+500 kHz
13
SW13,19=2
33 VIF VCO
freerun @JP
mode
FvcofJP 1
TP13 —
—
SW8,10=2 -500 0
+500 kHz
13
SW13,19=2
Rev.1.00, Aug.25.2003, page 8 of 16