HD74LV163A Datasheet, PDF (8/15 Pages) Hitachi Semiconductor – Synchronous 4-bit Binary Counter (Synchronous Clear)

HD74LV163A
Switching Characteristics (cont)
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
t_max
t_PLH/t_PHL
t_PLH/t_PHL
Count mode
t_PLH/t_PHL
Load mode
t_PLH/t_PHL
t_su
t_h
t_w
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM TO
Min Typ Max Min
Max
Unit Conditions (Input) (Output)
80 130 — 70
55 85 — 50
— 8.3 12.8 1.0
— 10.8 16.3 1.0
— 8.7 13.6 1.0
— 11.2 17.1 1.0
— 11.0 17.2 1.0
— 13.5 20.7 1.0
— 7.5 12.3 1.0
— 10.5 15.8 1.0
5.5 — — 6.5
—
—
15.0
18.5
16.0
19.5
20.0
23.5
14.5
18.0
—
MHz
ns
ns
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
Data before CLK ↑
8.0 — — 9.5
—
LOAD before CLK ↑
7.5 — — 9.0
—
ENT, ENP before
CLK ↑
4.0 — — 4.0
—
CLR before CLK ↑
1.0 — — 1.0
—
ns
1.0 — — 1.0
—
CLR after CLK ↑
5.0 — — 5.0
—
ns
CLK H or L
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
t_max
t_PLH/t_PHL
t_PLH/t_PHL
Count mode
t_PLH/t_PHL
Load mode
t_PLH/t_PHL
t_su
t_h
t_w
Ta = 25°C
Min Typ
135 185
95 125
— 4.9
— 8.7
— 4.9
— 6.4
— 6.2
— 7.7
— 4.9
— 6.4
4.5 —
5.0 —
5.0 —
3.5 —
1.0 —
1.5 —
5.0 —
Ta = –40 to 85°C
Test
V_CC = 5.0 ± 0.5 V
FROM TO
Max Min
Max
Unit Conditions (Input) (Output)
— 115
— 85
8.1 1.0
10.1 1.0
8.1 1.0
10.1 1.0
10.3 1.0
12.3 1.0
8.1 1.0
10.1 1.0
— 4.5
—
—
9.5
11.5
9.5
11.5
12.0
14.0
9.5
11.5
—
MHz
ns
ns
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
CLK
Q
CLK
Carry
CLK
Carry
ENT
Carry
Data before CLK ↑
— 6.0
—
LOAD before CLK ↑
— 6.0
—
ENT, ENP before
CLK ↑
— 3.5
—
CLR before CLK ↑
— 1.0
—
ns
— 1.5
—
CLR after CLK ↑
— 5.0
—
ns
CLK H or L
Rev.5.00 Jun. 04, 2004 page 8 of 14