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HD74LS161A Datasheet, PDF (8/11 Pages) Hitachi Semiconductor – Synchronous 4-bit Binary Counters(direct clear)
HD74LS161A
Waveforms 2
tPLH, tPHL, (Clock→Q)
tTLH
tTHL
90% 90%
3V
Clock
10% 10%
1.3V
1.3V
0V
tTLH
tTHL
Data Inputs
A, B, C or D
90%
10%
90%
tPLH
10%
3V
0V
tPHL
Outputs
QA, QB, QC or QD
1.3V
VOH
1.3V
VOL
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input: PRR = 1 MHz, duty cycle 50%,
Data input: PRR = 500 kHz, duty cycle 50%
Waveforms 3
tPLH, tPHL, (Enable T→Ripple Carry)
tTLH
Enable T
10 %
90 %
1.3 V
tPLH
tTHL
90 %
1.3 V
10 %
tPHL
Carry
Output
1.3 V
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz
1.3 V
Waveforms 4
tPHL, (Clear→Q)
Clear
tTHL
tTLH
90%
1.3V
10% 10%
90%
1.3V
tw (CLR) ≥ 20ns
QA to QD
1.3V
tPHL
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns
3V
0V
VOH
VOH
3V
0V
VOH
VOL
Rev.2.00, Feb.18.2005, page 8 of 10