3803_15 Datasheet, PDF (79/138 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3803/3804 Group
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 72, 73, and Table 14. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 14).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 14, the BB flag set/
reset time.
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I²CIRQ” occurs to the CPU.
Table 14 START condition/STOP condition detecting conditions
Standard clock mode
High-speed clock mode
SCL release time SSC value + 1 cycle (6.25 µs) 4 cycles (1.0 µs)
Setup time
SSC value + 1 _{cycle < 4.0 µs (3.125 µs)}
2
2 cycles (0.5 µs)
Hold time
SSC value + 1 _{cycle < 4.0 µs (3.125 µs) 2 cycles (0.5 µs)}
2
BB flag set/
reset time
SSC
value
2
–1
+
2
cycles
(3.375
µs)
3.5 cycles (0.875 µs)
Note: Unit : Cycle number of internal clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I²C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
SCL
SDA
BB flag
SCL release time
Setup
time
Hold time
BB flag
set time
Fig. 72 START/STOP condition detecting timing diagram
SCL
SDA
BB flag
SCL release time
Setup
time
Hold time
BB flag
reset
time
Fig. 73 STOP condition detecting timing diagram
Rev.4.01 Nov 14, 2003 page 77 of 136