M37905M4C-XXXFP Datasheet, PDF (74/103 Pages) Renesas Technology Corp – 16-BIT CMOS MICROCOMPUTER

PRELIMINARY _{NSootimcee: pTahriasmisentroict} ^{alimfinitsalasrpeescuifbicjeactitotno. change.}
MITSUBISHI MICROCOMPUTERS
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 83 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf32, which is obtained by dividing
the peripheral devices’ clock f2 by 16; or clock Wf512, which is ob-
tained by doing it by 256. Bit 0 of the watchdog timer frequency se-
lect register (watchdog timer frequency select bit) shown in Figure 84
selects which clock is to be counted.
Wf512 is selected when this bit 0 is “0”, and Wf32 is selected when bit
0 is “1”. Bit 0 is cleared to “0” after reset.
FFF16 is set in the watchdog timer when “L” level voltage is applied
to pin RESET, STP instruction is executed, data is written to the
watchdog timer register (address 6016), or the most significant bit of
the watchdog timer becomes “0”.
After FFF16 is set in the watchdog timer, when the watchdog timer
counts Wf32 or Wf512 by 2048 counts, the most significant bit of the
watchdog timer becomes “0”, the watchdog timer interrupt request
bit is set to “1”, and FFF16 is set again in the watchdog timer.
In program coding, make sure that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“0”. If this routine is not executed owing to unexpected program ex-
ecution or others, the most significant bit of the watchdog timer be-
comes “0” and an interrupt is generated.
The microcomputer can generate a reset pulse by writing “1” to bit 6
(software reset bit) of processor mode register 0 in an interrupt rou-
tine and can be restarted.
The watchdog timer can also be used to return from the STP state,
where a clock has stopped its operation owing to the STP instruction
execution. For details, refer to the sections on the clock generating
circuit and standby function.
The watchdog timer stops its operation in the following cases, and at
this time, input to the watchdog timer is disabled:
• When the external area is accessed in the hold state
• In the wait mode
• In the stop mode
76543210
Address
Watchdog timer frequency select register 6116
Watchdog timer frequency select bit
0 : W f512
1 : W f32
Watchdog timer clock source select bits at STP
state termination
0 0 : fX32
0 1 : fX16
1 0 : fX128
1 1 : fX64
Fig. 84 Bit configuration of watchdog timer frequency select register
f2
Wait mode
Divided f(XIN)
fX16
fX32
fX64
fX128
1/16
Watchdog timer
frequency select bit
Wf32 ¹
1/16 ^Wf512
0
Watchdog timer
Watchdog timer
interrupt request
❈
Disables watchdog
timer (Note).
Stop mode
“FFF16” is set.
Watchdog timer clock source select Writing to watchdog
bits at STP state termination
timer register
RESET
STP instruction
• Watchdog timer register: address 6016
• Watchdog timer frequency select register: bit 0 at address 6116
• Watchdog timer clock source select bits at STP state termination: bits 6, 7 at address 6116
❈ When the most significant bit of the watchdog timer becomes “0”, this signal will be generated.
Note: During the stop mode and until the stop mode is terminated, setting for disabling the
watchdog timer is ignored.
Fig. 83 Block diagram of watchdog timer
73