R8C12 Datasheet, PDF (70/198 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / R8C /Tiny SERIES

R8C/12 Group
12.1 Timer (Timer X)
12.1.3 Event Counter Mode
_____
In this mode, the timer counts an external signal fed to INT1/CNTR0 pin (See “Table 12.4 Event
Counter Mode Specifications”). Figure 12.6 shows TXMR register in event counter mode.
Table 12.4 Event Counter Mode Specifications
Item
Specification
Count source
External signals fed to CNTR0 pin (Active edge is selected by program)
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
1/(n+1)(m+1) n: set value of PREX register, m: set value of TX register
Count start condition
Write “1” (count start) to TXS bit in TXMR register
Count stop condition
Write “0” (count stop) to TXS bit in TXMR register
Interrupt request
• When Timer X underflows [Timer X interrupt]
generation timing
_______
INT1/CNTR0 pin function Count source input (INT1 interrupt input)
CNTR0 pin function
Programmable I/O port
Read from timer
Count value can be read by reading TX register
Same applies to PREX register.
Write to timer
Value written to TX register is written to both reload register and counter.
Select function
Same applies to PREX register.
_____
• INT1/CNTR0 polarity switching function
Active edge of count source can be selected with R0EDG.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
00 00
10
Symbol
TXMR
Address
008B16
After reset
0016
Bit symbol
Bit name
Function
RW
TXMOD0 Operation mode
select bit 0, 1
b1 b0
1 0 : Event counter mode
RW
TXMOD1
RW
R0EDG
INT1/CNTR0 polarity _{0 : Rising edge}
switching bit⁽¹⁾
1 : Falling edge
RW
TXS
Timer X count
0 : Stops counting
start flag
1 : Starts counting
RW
TXOCNT Set to "0" in event counter mode
RW
TXMOD2 _{Set to "0" in event counter mode}
RW
TXEDG Set to "0" in event counter mode
RW
TXUND ^{Set to "0" in event counter mode}
RW
NOTES:
1. The IR bit in the INT1IC register may be set to “1” (interrupt requested) when the R0EDG bit is rewritten.
Refer to the paragraph 19.2.5 “Changing Interrupt Factor” in the Usage Notes Reference Book.
Figure 12.6 TXMR Register in Event Counter Mode
Rev.1.20 Jan 27, 2006 page 60 of 181
REJ09B0110-0120