M38049FFLSP Datasheet, PDF (70/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3804 Group (Spec.L)
• Bit 6: Communication mode specification bit (transfer
direction specification bit: TRX)
This bit decides a direction of transfer for data communication.
When this bit is “0”, the reception mode is selected and the data
of a transmitting device is received. When the bit is “1”, the
transmission mode is selected and address data and control data
are output onto the SDA in synchronization with the clock
generated on the SCL.
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
• This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
• When a STOP condition is detected.
• When writing “1” to this bit by software is invalid by the
START condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
• Bit 7: Communication mode specification bit (master/
slave specification bit: MST)
This bit is used for master/slave specification for data
communication. When this bit is “0”, the slave is specified, so
that a START condition and a STOP condition generated by the
master are received, and data communication is performed in
synchronization with the clock generated by the master. When
this bit is “1”, the master is specified and a START condition and
a STOP condition are generated. Additionally, the clocks
required for data communication are generated on the SCL.
This bit is set to “0” in one of the following conditions.
• Immediately after completion of the byte which has lost
arbitration when arbitration lost is detected
• When a STOP condition is detected.
• Writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• At reset
Note. START condition duplication preventing function
The MST, TRX, and BB bits is set to “1” at the same time after
confirming that the BB flag is “0” in the procedure of a START
condition occurrence. However, when a START condition by
another master device occurs and the BB flag is set to “1” imme-
diately after the contents of the BB flag is confirmed, the START
condition duplication preventing function makes the writing to the
MST and TRX bits invalid. The duplication preventing function
becomes valid from the rising of the BB flag to reception comple-
tion of slave address.
b7
b0
I²C status register
MST TRX BB PIN AL AAS AD0 LRB _{(S1: address 001316)}
Last receive bit (Note)
0: Last bit = “0”
1: Last bit = “1”
General call detecting flag
(Note)
0: No general call detected
1: General call detected
Slave address comparison flag
(Note)
0: Address disagreement
1: Address agreement
Arbitration lost detecting flag
(Note)
0: Not detected
1: Detected
SCL pin low hold bit
0: SCL pin low hold
1: SCL pin low release
Bus busy flag
0: Bus free
1: Bus busy
Communication mode
specification bits
0 0 : Slave receive mode
0 1 : Slave transmit mode
1 0 : Master receive mode
1 1 : Master transmit mode
Note: These bits and flags can be read out, but cannot be written.
Write “0” to these bits at writing.
Fig. 64 Structure of I²C status register
SCL
PIN
I²CIRQ
Fig. 65 Interrupt request signal generating timing
Rev.1.00 Oct 27, 2008 Page 68 of 128
REJ03B0266-0100