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| RMLV0416E_15 Datasheet, PDF (7/15 Pages) Renesas Technology Corp – 4Mb Advanced LPSRAM (256-kword × 16-bit) | |||
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RMLV0416E Series
Timing Waveforms
Read Cycle
A0~17
CS1#
tRC
Valid address
tAA
tACS1
t *14,15
CLZ1
tCHZ1 *13,14,15
CS2
LB#,UB#
WE#
VIH
WE# = âHâ level
OE#
I/O0~15
tACS2
tCLZ2*14,15
tBA
tBLZ *14,15
tCHZ2 *13,14,15
tBHZ *13,14,15
tOE
High impedance
tOLZ *14,15
tOHZ *13,14,15
tOH
Valid Data
Note
13. tCHZ1, tCHZ2, tBHZ and tOHZ are defined as the time when the I/O pins enter a high-impedance state and are not
referred to the I/O levels.
14. This parameter is sampled and not 100% tested
15. At any given temperature and voltage condition, tCHZ1 max is less than tCLZ1 min, tCHZ2 max is less than tCLZ2
min, tBHZ max is less than tBLZ min, and tOHZ max is less than tOLZ min, for any device.
R10DS0205EJ0100 Rev.1.00
2014.2.27
Page 7 of 13
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