R2J20601NP Datasheet, PDF (7/14 Pages) Renesas Technology Corp – Driver - MOS FET Integrated SiP (DrMOS)

R2J20601NP
Test Circuit
VB
VLDRV
VCIN
A ^IIN
A ^ILDRV
A ^ICIN
5 V pulse
VCIN VLDRV BOOT
DISBL#
VIN
Reg5V DrMOS VSWH
PWM
CGND GH
PGND
GL
Note: P_IN = I_IN × V_IN + I_LDRV × V_LDRV + I_CIN × V_CIN
POUT = IO × VO
Efficiency = POUT / PIN
PLOSS(DrMOS) = PIN – POUT
V VIN
Electric
load
IO
Averaging Average Output Voltage
circuit
V _VO
Rev.5.00 Apr 10, 2006 page 7 of 13