2SK3228_15 Datasheet, PDF (7/10 Pages) Renesas Technology Corp – Silicon N Channel MOS FET High Speed Power Switching

2SK3228
Reverse Drain Current vs.
Source to Drain Voltage
100
80
60
10 V
5V
40
V_GS = 0, –5 V
20
Pulse Test
0
0
0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage V_SD (V)
Maximum Avalanche Energy vs.
Channel Temperature Derating
200
I_AP = 50 A
160
V_DD = 25 V
duty < 0.1 %
Rg ≥ 50 Ω
120
80
40
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Normalized Transient Thermal Impedance vs. Pulse Width
3
D=1
1
0.5
Tc = 25°C
0.3
0.2
0.1
0.1
0.05
θch – c (t) = γ s (t) • θch – c
θch – c = 1.25°C/W, Tc = 25°C
0.03
0.02
0.01
1shot
pulse
P_DM
D = ^PW
T
PW
T
0.01
10 µ
100 µ
1m
10 m
100 m
1
10
Pulse Width PW (S)
Vin
15 V
Avalanche Test Circuit
V_DS
Monitor
L
I_AP
Monitor
Rg
D.U.T
V_DD
50 Ω
Avalanche Waveform
E_AR =
1
2
• L • I_AP2 •
V_DSS
V_DSS – V_DD
I_AP
I_D
V_(BR)DSS
V_DS
V_DD
0
Rev.4.00 May 15, 2006 page 5 of 7