H838086R Datasheet, PDF (65/697 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Super Low Power Series

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/38086R Group ........................................................... 3
Figure 1.2 Pin Assignment of H8/38086R Group (FP-80A, TFP-80C)....................................... 4
Figure 1.3 Pin Assignment of H8/38086R Group (TLP-85V)..................................................... 5
Figure 1.4 Pad Assignment of HCD64F38086R (Top View)...................................................... 9
Figure 1.5 Pad Assignment of HCD64338086R (Top View) .................................................... 13
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................ 26
Figure 2.2 CPU Registers .......................................................................................................... 27
Figure 2.3 Usage of General Registers ...................................................................................... 28
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................ 29
Figure 2.5 General Register Data Formats (1) ........................................................................... 31
Figure 2.5 General Register Data Formats (2) ........................................................................... 32
Figure 2.6 Memory Data Formats.............................................................................................. 33
Figure 2.7 Instruction Formats................................................................................................... 44
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................ 48
Figure 2.9 On-Chip Memory Access Cycle............................................................................... 51
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access).................................... 52
Figure 2.11 CPU Operating States............................................................................................... 53
Figure 2.12 State Transitions ....................................................................................................... 54
Figure 2.13 Example of Timer Configuration with Two Registers Allocated
to Same Address....................................................................................................... 55
Section 3 Exception Handling
Figure 3.1 Reset Exception Handling Sequence........................................................................ 64
Figure 3.2 Interrupt Sources and their Numbers........................................................................ 65
Figure 3.3 Stack Status after Exception Handling ..................................................................... 66
Figure 3.4 Operation when Odd Address is Set in SP ............................................................... 68
Figure 3.5 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag Clearing
Procedure.................................................................................................................. 71
Section 4 Interrupt Controller
Figure 4.1 Block Diagram of Interrupt Controller ..................................................................... 73
Figure 4.2 Flowchart of Procedure Up to Interrupt Acceptance ................................................ 92
Figure 4.3 Interrupt Exception Handling Sequence................................................................... 93
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