3804H Datasheet, PDF (63/116 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

3804 Group (Spec. H)
[I²C Status Register (S1)] 001316
The I²C status register (S1: address 001316) controls the I²C-BUS
interface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I²C data shift register
(S0: address 001116).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call^✽
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
✽General call: The master transmits the general call address “0016” to all
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
➀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-or-
der 7 bits of the I²C slave address register.
• A general call is received.
➁ In the slave receive mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition:
• When the address data is compared with the I²C slave ad-
dress register (8 bits consisting of slave address and RWB
bit), the first bytes agree.
➂ This bit is set to “0” by executing a write instruction to the I²C data
shift register (S0: address 001116) when ES0 is set to “1” or reset.
•Bit 3: Arbitration lost^✽ detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
The AL bit is set to “0” in one of the following conditions:
•Executing a write instruction to the I²C data shift register (S0: ad-
dress 001116)
•When the ES0 bit is “0”
•At reset
✽Arbitration lost :The status in which communication as a master is dis-
abled.
Rev.1.01 Jan 25, 2005 page 63 of 114
REJ03B0131-0101Z
•Bit 4: SCL pin low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 61 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
• Executing a write instruction to the I²C data shift register (S0:
address 001116). (This is the only condition which the prohibition
of the internal clock is released and data can be communicated
except for the start condition detection.)
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN bit by software
The PIN bit is set to “0” in one of the following conditions:
• Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately af-
ter completion of slave address agreement or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately af-
ter completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the START condition, and is set to “0” by detecting the
STOP condition. The condition of these detecting is set by the
START/STOP condition setting bits (SSC4–SSC0) of the I²C
START/STOP condition control register (S2D: address 001616).
When the ES0 bit of the I²C control register (bit 3 of S1D, address
001416) is “0” or reset, the BB flag is set to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.