R8C18 Datasheet, PDF (60/257 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/1x SERIES

R8C/18 Group, R8C/19 Group
7. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset⁽⁸⁾
VW2C
0037h
00h
Bit Symbol
Bit Name
Function
RW
Voltage monitor 2 interrupt/reset 0 : Disable
VW2C0 _{enable bit(6, 10)}
1 : Enable
RW
Voltage monitor 2 digital filter
0 : Digital filter enabled mode
disable mode select bit⁽²⁾
(digital filter circuit enabled)
VW2C1
1 : Digital filter disabled mode
RW
(digital filter circuit disabled)
Voltage change detection flag^{(3, 4, 8)} 0 : Not detected
VW2C2
1 : Vdet2 crossing detected
RW
WDT detection flag^{(4, 8)}
0 : Not detected
VW2C3
1 : Detected
RW
Sampling clock select bits
b5 b4
VW2F0
0 0 : fRING-S divide by 1
RW
0 1 : fRING-S divide by 2
VW2F1
1 0 : fRING-S divide by 4
1 1 : fRING-S divide by 8
RW
Voltage monitor 2 circuit mode
0 : Voltage monitor 2 interrupt mode
VW2C6 _{select bit(5)}
1 : Voltage monitor 2 reset mode
RW
Voltage monitor 2 interrupt/reset 0 : When VCC reaches Vdet2 or above.
generation condition select bit^{(7, 9)} 1 : When VCC reaches Vdet2 or below .
VW2C7
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to this register.
When rew riting the VW2C register, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after rew riting the VW2C
register.
2. When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite 0 to the VW2C1bit before
w riting 1.
3. This bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. This bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enabled reset).
6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, or voltage monitor 2
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or
below ). (Do not set to 0.)
10. Set the VW2C0 bit to 0 (disabled) w hen the VCA13 bit in the VCA1 register is set to 1 (VCC ≥ Vdet2 or voltage
detection 2 circuit disabled), the VW2C1 bit is set to 1 (digital filter disabled mode), and the VW2C7 bit is set to 0
(w hen VCC reaches Vdet2 or above).
Set the VW2C0 bit to 0 (disabled) w hen the VCA13 bit is set to 0 (VCC < Vdet2), the VW2C1 bit is set to 1 (digital
filter disabled mode), and the VW2C7 bit is set to 1 (w hen VCC reaches Vdet2 or below ).
Figure 7.6 VW2C Register
Rev.1.30 Apr 14, 2006 Page 45 of 233
REJ09B0222-0130