RNA51XX Datasheet, PDF (6/12 Pages) Renesas Technology Corp – CMOS system.RESET IC

RNA51xx Series
1000
100
10
1
0.1
1
10
100
1000
External Capacitor CD (nF)
Figure 1 Dependence of MR pin minimum input low pulse width and external capacitor CD
Pin Description
PIN
NAME
FUNCTION
1
VOUT VOUT changes from high to low whenever VDD drops below –V_TH.
A pull-up resistor from 470 kΩ to 1 MΩ should be used on this pin for open-drain output.
2
VDD Supply voltage and input for voltage detector.
A decoupling capacitor with excellent high frequency characteristics should be placed near VDD
pin and connected between VDD and GND pin.
3
GND Ground
4
MR Active-low Manual Reset Input. VOUT is low-level while MR is low.
Once MR is disabling, VOUT turn to high-level after delay time.
MR pin is internally pulled up to VDD through 2 MΩ.
5
CD Connect capacitor between CD and GND pin to set programmable delay time.
Ceramic capacitor from 100 pF to 0.1 µF is recommended.
REJ03D0505-0300 Rev.3.00 Oct 10, 2008
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