HD74LV2GT74A Datasheet, PDF (6/10 Pages) Renesas Technology Corp – Single D-type Flip Flops with Preset and Clear / CMOS Logic Level Shifter

HD74LV2GT74A
Switching Characteristics
• V_CC = 3.3 ± 0.3 V
Item
Symbol
Maximum clock f_max
frequency
Propagation t_PLH
delay time t_PHL
Setup time t_su
Hold time
t_h
Pulse width t_w
T_a = 25°C
Min Typ
80 140
50 90
— 7.0
— 8.0
— 9.0
— 10.0
6.0 —
5.0 —
0.5 —
6.0 —
6.0 —
Max
—
—
12.5
12.0
16.0
15.5
—
—
—
—
—
T_a = –40 to 85°C
Test
FROM TO
Min Max ^{Unit Conditions (Input) (Output)}
70
—
MHz C_L = 15 pF
45
—
C_L = 50 pF
1.0 14.5 ns C_L = 15 pF PRE/CLR Q or Q
1.0 14.0
CLK
1.0 18.0
1.0 17.5
C_L = 50 pF PRE/CLR Q or Q
CLK
7.0 —
ns
D
5.0 —
PRE or CLR inactive
0.5 —
ns
7.0 —
ns
PRE or CLR “L”
7.0 —
CLK “H” or “L”
• V_CC = 5.0 ± 0.5 V
Item
Symbol
Maximum clock f_max
frequency
Propagation t_PLH
delay time t_PHL
Setup time t_su
Hold time
t_h
Pulse width t_w
T_a = 25°C
Min Typ
130 180
90 140
— 5.0
— 5.6
— 6.6
— 7.2
5.0 —
3.0 —
0.5 —
5.0 —
5.0 —
Max
—
—
7.7
7.3
9.7
9.3
—
—
—
—
—
T_a = –40 to 85°C
Test
FROM TO
Min Max ^{Unit Conditions (Input) (Output)}
110 —
75
—
1.0 9.0
1.0 8.5
MHz C_L = 15 pF
C_L = 50 pF
ns C_L = 15 pF
PRE/CLR Q or Q
CLK
1.0 11.0
1.0 10.5
C_L = 50 pF PRE/CLR Q or Q
CLK
5.0 —
ns
D
3.0 —
PRE or CLR inactive
0.5 —
ns
5.0 —
ns
PRE or CLR “L”
5.0 —
CLK “H” or “L”
Rev.2.00, Oct.17.2003, page 6 of 9