HD74LV1G125A_15 Datasheet, PDF (6/9 Pages) Renesas Technology Corp – Bus Buffer Gate with 3–state Output

HD74LV1G125A
Test Circuit
V_CC
Input
Pulse Generator
Z OUT = 50 Ω
V_CC
Output
1 k Ω _S1
C_L =
15 or 50 pF
OPEN
*1 See under table
GND
TEST
t_PLH / t _PHL
t_ZH/ t _HZ
t_ZL / t _LZ
S1
OPEN
GND
V_CC
Note: 1. C_L includes probe and jig capacitance.
Waveform
• Waveforms - 1
t_r
Input A
10 %
90 %
50%
t_PLH
t_f
90 %
50%
10 %
t_PHL
Output Y
50%
50%
V_CC
GND
V_OH
V_OL
• Waveforms - 2
t_f
Input OE
90 %
50%
10 %
t_ZL
Waveform - A
50%
t_ZH
Waveform - B
50%
t_r
10 %
90 %
50%
t_LZ
t_HZ
V_OL + 0.3 V
V_OH – 0.3 V
V_CC
GND
V_CC
V_OL
V_OH
GND
Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω, t_r ≤ 3 ns, t_f ≤ 3 ns.
2. Waveform - A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
R04DS0025EJ0800 Rev.8.00
Jan 10, 2014
Page 6 of 8