HD74LS669 Datasheet, PDF (6/9 Pages) Hitachi Semiconductor – Synchronous Up/Down 4-bit Binary Counters

HD74LS669
Waveforms 1
Clock
Load
t_THL
t_TLH
90%
1.3V
10% 10%
t_{w (CK)}
t_su
1.3V
90%
1.3V
1.3V
t_{w (CK)}
t_su
t_h
1.3V
1.3V
Data Inputs
A, B, C, D
Enable P
or
Enable T
t_su
1.3V
t_h
1.3V
t_su
1.3V
t_su
t_h
Up/Down
1.3V
1.3V
3V
1.3V
0V
3V
0V
3V
0V
t_h
3V
1.3V
0V
t_su
t_h
3V
1.3V
1.3V
0V
Notes:
Enable T
Input
1.3V
3V
1.3V
0V
t_PHL
t_PLH
Ripple
Carry
1.3V
Output
1.3V
V_OH
V_OL
1. t_PLH and t_PHL from enable T input to ripple carry output assume that the counter is at the
maximum count (Q_A through Q_D high).
2. Propagation delay time from up / douwn to ripple carry must be measured with the counter at
either aminimum or a maximum count. As the logic level of the up / down input is changed, the
riiple carry output will follow. If the count is minimum (0) are ripple carry output transition will
be in phase. If the count is macimum (15) the ripple carry output will be out of phase.
3. Input pulse; t_TLH ≤ 15 ns, t_THL ≤ 6 ns, PRR = 1 MHz
Rev.2.00, Feb.18.2005, page 6 of 8