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HD74HC670 Datasheet, PDF (6/9 Pages) Hitachi Semiconductor – 4-by-4 Register File (with 3-state outputs)
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HD74HC670
Test Circuit
VCC
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
VCC
Output
GR
GW Q1 to Q4
RA
RB
WA
WB
D1 to D4
1 k Ω S1
CL =
50 pF
OPEN
GND
VCC
TEST
tPLH / t PHL
tZH/ t HZ
tZL / t LZ
S1
OPEN
GND
VCC
Note : 1. CL includes probe and jig capacitance.
Waveforms
• Waveform – 1
tr
tf
90 %
90 %
VCC
WA or WB
50 %
50 %
10 %
tsu
10 %
th
0V
tf
tr
Data
90 %
90 %
VCC
50 %
50 %
D1 to D4
10 %
tsu
10 %
th
0V
tf
tr
90 %
90 %
VCC
GW
50 %
50 %
10 % 10 %
0V
tw
tr
tf
RA or RB
tlatch
90 % 90 %
VCC
50 %
50 %
10 %
10 %
0V
tPHL
tPLH
Q1 to Q4
50 % 50 %
10 % 10 %
90 %
VOH
VOL
tTHL
tTLH
Note : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
Rev.2.00 Mar 30, 2006 page 6 of 8
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