HD74HC165_15 Datasheet, PDF (6/10 Pages) Renesas Technology Corp – Parallel-load 8-bit Shift Register

HD74HC165
Switching Characteristics
Item
Maximum clock
frequency
Propagation delay
time
Setup time
Removal time
Hold time
Pulse width
Output rise/fall
time
Input capacitance
Symbol V_CC (V)
f_max
2.0
4.5
6.0
t_PLH, t_PHL 2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
t_su
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
t_rem
2.0
4.5
6.0
t_h
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
t_w
2.0
4.5
6.0
t_TLH, t_THL 2.0
4.5
6.0
Cin
—
Ta = 25°C
Min Typ Max
—— 5
— — 27
— — 32
— — 150
— 21 30
— — 26
— — 160
— 23 32
— — 27
— — 150
— 21 30
— — 26
100 — —
20 –3 —
17 — —
100 — —
20 3 —
17 — —
100 — —
20 — —
17 — —
100 — —
20 6 —
17 — —
5 ——
5 –3 —
5 ——
5 ——
5
3—
5 ——
5 ——
5 ——
5 ——
80 — —
16 6 —
14 — —
— — 75
— 5 15
— — 13
— 5 10
(C_L = 50 pF, Input t_r = t_f = 6 ns)
Ta = –40 to +85°C
Min Max Unit
Test Conditions
—
4 MHz
—
21
—
25
—
190 ns Clock to Q_H or Q_H
—
38
—
33
—
200 ns Shift/Load to Q_H or Q_H
—
40
—
34
—
190 ns H to Q_H or Q_H
—
38
—
33
125
—
ns Parallel data inputs to
25
—
Shift/Load
21
—
125
—
ns Serial input to Clock
25
—
21
—
125
—
ns Shift/load to Clock
25
—
21
—
125
—
ns Clock to Clock inhibit or
25
—
Clock inhibit to Clock
21
—
5
—
ns Shift/Load to parallel data
5
—
input
5
—
5
—
ns Clock to Serial input
5
—
5
—
5
—
ns Clock to Shift/Load
5
—
5
—
100
—
ns Clock, Shift/Load
20
—
17
—
—
95 ns
—
19
—
16
—
10 pF
Rev.3.00, Jan 31, 2006 page 4 of 7