2SJ555_15 Datasheet, PDF (6/10 Pages) Renesas Technology Corp – Silicon P Channel MOS FET

2SJ555
Static Drain to Source on State Resistance
vs. Temperature
50
Pulse Test
40
V_GS = –4 V
30
I_D = –50 A _{–20 A}
–10 A
20
–50 A
–10 A, –20 A
10
–10 V
0
–40 0
40 80 120 160
Case Temperature Tc (°C)
1000
500
Body-Drain Diode Reverse
Recovery Time
200
100
50
20
di / dt = 50 A / µs
V_GS = 0, Ta = 25°C
10
–0.1 –0.3 –1 –3 –10 –30 –100
Reverse Drain Current I_DR (A)
Dynamic Input Characteristics
0
0
V_DD = –10 V
–25 V
–20
–50 V
–4
–40
V_GS
–8
V_DS
–60
V_DD = –50 V
–25 V
–12
–10 V
–80
–16
I_D = –60 A
–100
0
80 160 240 320
Gate Charge Qg (nc)
–20
400
Forward Transfer Admittance vs.
Drain Current
100
Tc = –25°C
30
25°C
10
75°C
3
1
0.3
V_DS = –10 V
Pulse Test
0.1
–0.1 –0.3 –1 –3 –10 –30 –100
Drain Current I_D (A)
50000
20000
10000
5000
Typical Capacitance vs.
Drain to Source Voltage
V_GS = 0
f = 1 MHz
Ciss
2000
1000
500
Coss
200
100
0
Crss
–10 –20 –30 –40 –50
Drain to Source Voltage V_DS (V)
1000
500
200
100
50
Switching Characteristics
td(off)
tf
tr
td(on)
20
10
–0.1 –0.3
V_GS = –10 V, V_DD = –30 V
PW = 10 µs, duty ≤ 1 %
–1 –3 –10 –30 –100
Drain Current I_D (A)
Rev.3.00 Sep 07, 2005 page 4 of 7