2SJ526_15 Datasheet, PDF (6/10 Pages) Renesas Technology Corp – Silicon P Channel MOS FET

2SJ526
Static Drain to Source on State Resistance
vs. Temperature
0.5
Pulse Test
0.4
0.3
I_D = –5 A
0.2 ^{VGS = –4 V}
–2 A
–1 A
0.1
0
–40
–10 V
0
40
–1 A, –2 A
–5 A
80 120 160
Case Temperature Tc (°C)
Body-Drain Diode Reverse
Recovery Time
500
Pulse Test
200
100
50
20
10
5
–0.1 –0.2 –0.5
di / dt = 50 A / µs
V_GS = 0, Ta = 25°C
–1 –2 –5 –10
Reverse Drain Current I_DR (A)
Dynamic Input Characteristics
0
0
V_DD = –10 V I_D = –10 A
–25 V
–20
–50 V
–4
–40
V_GS
–8
V_DS
–60
–12
V_DD = –50 V
–25 V
–80
–10 V
–16
–100
0
8
16 24 32
Gate Charge Qg (nc)
–20
40
Forward Transfer Admittance vs.
Drain Current
20
10
Tc = –25°C
5
25°C
2
75°C
1
0.5
0.2
–0.1 –0.2 –0.5 –1
V_DS = –10 V
Pulse Test
–2 –5 –10
Drain Current I_D (A)
2000
1000
500
Typical Capacitance vs.
Drain to Source Voltage
Ciss
200
Crss
100
50
Coss
20 _{VGS = 0}
f = 1 MHz
10
0 –10 –20 –30 –40 –50
Drain to Source Voltage V_DS (V)
1000
Switching Characteristics
300
td(off)
100
tf
30
tr
td(on)
10
3
1
–0.1 –0.2
V_GS = –10 V, V_DD = –30 V
PW = 5 µs, duty ≤ 1 %
–0.5 –1 –2 –5 –10
Drain Current I_D (A)
Rev.6.00 Jun 05, 2006 page 4 of 7