R5F52108ADFP_11 Datasheet, PDF (56/146 Pages) Renesas Technology Corp – Renesas MCUs

Under development ^{Preliminary document}
Specifications in this document are tentative and subject to change.
RX210 Group
2. CPU
(d) When the load data is not used by the subsequent instruction
When the load data is not used by the subsequent instruction, the subsequent operations are in fact executed earlier and
the operation processing ends (out-of-order completion).
MOV [R1], R2
IF
D
E
M
M
M WB
ADD R4, R5
IF
D
E WB
SUB R6, R7
IF
D
E WB
Figure 2.25 When Load Data is not Used by the Subsequent Instruction
(mop) load
(mop) add
(mop) sub
2.8.3
Calculation of the Instruction Processing Time
Though the instruction processing time of the CPU varies according to the pipeline processing, the approximate time can
be calculated in the following methods.
 Count the number of cycles (see Table 2.13 and Table 2.14)
 When the load data is used by the subsequent instruction, the number of cycles described as “latency” is counted as
the number of cycles for the memory load instruction. For the cycles other than the memory load instruction, the
number of cycles described as “throughput” is counted.
 If the instruction fetch stall is generated, the number of cycles increments.
 Depending on the system configuration, multiple cycles are required for the memory access.
R01DS0041EJ0090 Rev.0.90
Aug 10, 2011
Page 56 of 144