M37274MA Datasheet, PDF (56/132 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37274MA-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
7
0
OSD control register
(OC : address 00CE16)
OSD control bit (Note 1)
0 : All-blocks display off
1 : All-blocks display on
Scan mode selection bit
0 : Normal scan mode
1 : Bi-scan mode
Border type selection bit
0 : All bordered
1 : Shadow bordered (Note 2)
Flash mode selection bit
0 : Color signal of character
background part does not
flash
1 : Color signal of character
background part flashes
Automatic solid space control
bit
0 : OFF
1 : ON
Window control bit
0 : OFF
1 : ON
Layer mixing control bits (Note 3)
b7 b6
0 0 : Logical sum (OR) of
layer 1’s color and
layer 2’s color
0 1 : Layer 1’s color has priority
1 0 : Layer 2’s color has priority
1 1 : Do not set
Notes 1 : Even this bit is switched during display, the display screen
remains unchanged until a rising (falling) of the next V SYNC.
2 : Shadow border is output at right and bottom side of the font.
3 : Set “00” during displaying extra fonts.
Fig. 55. OSD Control Register
7
0
Block control register i
(i = 1 to 12)
(BCi : addresses 00D016 to 00BF)
Display mode selection bits
b1 b0
0 0 : Display OFF
0 1 : OSD mode
1 0 : CC mode
1 1 : EXOSD mode
Border control bit
0 : Border OFF
1 : Border ON
Dot size selection bit
Refer to Table 12.
Pre-divide ratio • layer selection
bits
Refer to Table 12.
OUT 2 output control bit (Note)
0 : OUT2 output OFF
1 : OUT2 output ON
Notes 1: Bit RC 14 of OSD RAM controls OUT1 output
when bit 7 is “0.”
Bit RC 14 of OSD RAM controls OUT2 output
when bit 7 is “1.”
2: Note that EPROM version the block control registers
at addresses 00D0 16 to 00DF16 when programming.
Fig. 56. Block Control Registers
Table 12. Setting Value of Block Control Registers
Pre-divide
b6 b5 b4 b3 CS6
Ratio
Dot Size Display Layer
00
1TC ! 1/2H
01
00
—
10
11
00
!1
1TC ! 1H
2TC ! 2H
3TC ! 3H
1TC ! 1/2H
01
01
—
10
!2
1TC ! 1H
2TC ! 2H
Layer 1
11
00
3TC ! 3H
1TC ! 1/2H
01
10
—
10
!3
1TC ! 1H
2TC ! 2H
11
—0
11
0
—1
00
01
11
1
10
3TC ! 3H
!1
1TC ! 1/2H
1TC ! 1H
1TC ! 1/2H
Layer 2
!2
1TC ! 1H
1.5TC ! 1/2H
11
1.5TC ! 1H
Notes 1: CS6 : Bit 6 of clock control register (Address 021616)
2: TC : OSD clock cycle divided in the pre-divide circuit
3: H : HSYNC
55