H83397 Datasheet, PDF (537/747 Pages) Renesas Technology Corp – Single-Chip Microcomputer

Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit in FLMCR1. (Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.)
Bit 1: ESU
0
1
Description
Erase setup cleared
Erase setup
[Setting condition]
When SWE = 1
(Initial value)
Bit 0—Program Setup (PSU): Prepares for a transition to program mode. Set this bit to 1 before
setting the P bit in FLMCR1. (Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.)
Bit 0: PSU
0
1
Description
Program setup cleared
Program setup
[Setting condition]
When SWE = 1
(Initial value)
21.2.3 Erase Block Register 2 (EBR2)
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
1
0
0
0
Read/Write R/W* R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: The FLSHE bit in WSCR must be set to 1 in order for this register to be accessed.
* Writes to bit 7 are invalid in mode 2.
EBR2 is an 8-bit register that designates flash-memory erase blocks for erasure. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when the
SWE bit in FLMCR1 is not set. When a bit in EBR2 is set to 1, the corresponding block can be
erased. Other blocks are erase-protected. Only one bit should be set in EBR2; do not set two or
more bits. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 21.5.
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