HS0005KCU11H Datasheet, PDF (51/56 Pages) Renesas Technology Corp – SuperH™ Family E10A-USB Emulator

SuperH™ Family E10A-USB Emulator
Section 2 Software Specifications when Using the SH7785
Table 2.12 shows the measurement items and methods that are mainly used.
Table 2.12 Main Measurement Items
Main Measurement Item
Elapsed time
Number of execution instructions
Number of interrupts accepted
Number of instruction fetches (for
both cache and non-cache)
Instruction-cache hit ratio
Number of operand accesses (for
both cache and non-cache)
Operand-cache hit ratio (read)
Operand-cache hit ratio (write)
Operand-cache hit ratio
System bus: occupied rate of
request bus
System bus: occupied rate of
response bus
Measurement Method
Number of elapsed cycles x CPU clock cycles
Number of valid instructions issued + number of cases of
simultaneous execution of two instructions
Number of exceptions accepted
Number of memory accesses in an opcode
(Number of instruction-cache accesses– instruction-cache
miss counts)/instruction-cache access counts
Number of memory accesses in an operand (read) + number
of memory accesses in an operand (write)
(Number of operand-cache accesses (read) – number of
operand-cache misses (read))/number of operand-cache
accesses (read)
(Number of operand-cache accesses (write) – number of
operand-cache misses (write))/ number of operand-cache
accesses (write)
(Number of operand-cache accesses (read) + number of
operand-cache accesses (write) – number of operand-cache
misses (read) – number of operand-cache misses
(write))/(number of operand-cache accesses (read) + number
of operand-cache accesses (write))
(The equivalent CPU clock value of the number of
requests)/number of elapsed cycles
(The equivalent CPU clock value of the number of
responses)/number of elapsed cycles
R20UT2166EJ0200 Rev.2.00
Aug 09, 2012
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