UPC3250T7L Datasheet, PDF (5/18 Pages) Renesas Technology Corp – SiGe CMOS/BiCMOS Integrated Circuit

μPC3250T7L
ELECTRICAL CHARACTERISTICS
(T_A = +25°C, V_CCRF = V_CCIF = V_DDPLL = +3.3 V, G_SW = +3.3 V, Z_S = Z_L = 50 Ω, f_xtal = 25 MHz,
unless otherwise specified)
Parameter
Symbol
Test Conditions
MIN. TYP. MAX. Unit
Conversion Gain 1^{Note 1}
Conversion Gain 2^{Note 1}
Conversion Gain 3^{Note 1}
POLA control Threshold
Voltage 1^{Note 1}
POLA control Threshold
Voltage 2^{Note 1}
(Channel selection )
TONE control signal Threshold
Voltage^{Note 1}
(Channel selection)
Drain Voltage H^{Note 1, 2}
Drain Voltage V^{Note 1, 2}
Drain Voltage 1^{Note 1, 2}
G_conv1
G_conv2
G_conv3
V_{th_POLA}1
V_{th_POLA}2
f_LO = 9.75 GHz, f_IF = 1.5 GHz,
P_in = −50 dBm
f_LO = 10.6 GHz, f_IF = 1.5 GHz,
P_in = −50 dBm
f_LO = 10.75 GHz, f_IF = 1.5 GHz,
P_in = −50 dBm
Power Save mode to Normal mode
Dividing resistor : 8.2 kΩ/51 kΩ
Vertical mode to Horizontal mode
Dividing resistor : 8.2 kΩ/51 kΩ
V_{th_TONE}
V_DH
V_DV
V_D1
Low band to High band
f_TONE = 22 kHz, Duty Cycle = 50%,
Pulse wave
Divider capacitor : 0.1 μF/0.1 μF
V_POLA = 18 V, I_D = 10 mA,
R_cal = 22 kΩ
V_POLA = 13 V, I_D = 10 mA,
R_cal = 22 kΩ
I_D = 10 mA, R_cal = 22 kΩ
37
41
45
dB
37
41
45
dB
37
41
45
dB
3.6
−
7.0
V
15.2
15.7
16.2
V
0.1
0.15
0.35 V_p-p
1.8
2.0
2.2
V
1.8
2.0
2.2
V
1.8
2.0
2.2
V
Drain Voltage 2^{Note 1, 2}
V_D2
I_D = 10 mA, R_cal = 22 kΩ
1.8
2.0
2.2
V
Drain Current H^{Note 1, 2}
I_DH
V_POLA = 18 V, R_cal = 22 kΩ
8.5
10
11.5 mA
Drain Current V^{Note 1, 2}
I_DV
V_POLA = 13 V, R_cal = 22 kΩ
8.5
10
11.5 mA
Drain Current 1^{Note 1, 2}
I _D1
R_cal = 22 kΩ
8.5
10
11.5 mA
Drain Current 2^{Note 1, 2}
I _D2
R_cal = 22 kΩ
8.5
10
11.5 mA
Gate Voltage H^{Note 1, 2}
of FET OFF mode
Gate Voltage V^{Note 1, 2}
of FET OFF mode
V_GH
V_GV
V_POLA = 13 V
V_POLA = 18 V
−2.0
−2.5
−3.0
V
−2.0
−2.5
−3.0
V
Notes: 1
2
See the evaluation (application) circuit.
The detail connection of pin 20 (TonePol) is shown in the evaluation circuit.
This pin cannot be directly connected to 13 V/18 V polarity control voltage.
The polarity control voltage must be divided to a low voltage by the external resistors.
See the graph of “R_cal vs. I_DFET, V_DFET.” FET’s drain current can be adjusted by the external resisters (R_cal).
R09DS0052EJ0100 Rev.1.00
Oct 23, 2012
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