RNA52A10T_15 Datasheet, PDF (5/12 Pages) Renesas Technology Corp – Dual CMOS system–RESET IC

RNA52A10T
Electrical Characteristics
(Ta = 25°C, unless otherwise noted)
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Test
Circuit
Supply voltage
V_DD
1.4
—
5.5
V
—
Current consumption
I_DD
—
1.1
19
μA ^{VDD = 5.5 V}
V_i1 = V _i2 = 5.5 V
1
Reference voltage
V_REF
0.95
1.00
1.05
V V_DD = 3.3 V
2
Reference voltage temperature
ΔV_REF
ppm
coefficient
V_REF ⋅ΔT_a
—
±100
—
°C ^Ta ^{= –40 to 85°C}
2
(Reference value for design)
Vi1, Vi2 input
hysteresis voltage
28.5
60
94.5
V_HYS
(V_REF×3%) (V_REF×6%) (V_REF×9%) ^{mV VDD = 3.3 V}
2
Vi1, Vi2 input current
I_IN
—
0.6
2.2
μA ^{VDD = 5.5 V}
V_i1 = V _i2 = 5.5 V
3
CD input threshold voltage
V_DLY
V_DD×0.43 V_DD×0.63 V_DD×0.83
V
V_DD = 3.3 V
V_i1 = V _i2 = 1.2 V
4
V_DD = 1.4V
—
0.05
0.15
V V_i1 = V _i2 = 0 V
5
Vo1, Vo2
low-level output voltage
V_OL
I_OL = 0.5 mA
V_DD = 3.3V
—
0.15
0.35
V V_i1 = V _i2 = 0 V
6
I_OL = 5 mA
Vo1, Vo2
output leakage current
I_LK
—
—
100
nA ^{VDD = VO1 = VO2 = 5.5 V}
7
V_i1 = V _i2 = 1.2 V
Incomplete
Vo2
discharge of
T_DLY
1.1
capacity CD
11
17
ms
V_DD = 3.3 V
8
Delay time ^Note1 complete
V_i2 = 0 V→1.2 V
discharge of
T_DLY0
7
11
17
ms ^{CD = 0.3 μF, RD = 39 kΩ}
8
capacity CD
Vo1
Rise response time
T_PLH
—
30
300
μs ^{VDD = 3.3 V}
V_i1 = 0 V→1.2 V
9
Vo1, Vo2
fall response time
T_PHL
—
V_DD = 3.3 V
30
800
μs V_i1 = V_i2 = 1.2 V→0 V
10
C_D = 0.3 μF, R_D = 39 kΩ
MR low-level input voltage
V_IL
—
—
V_DD×0.2
V
V_DD = 3.3 V
V_i1 = V _i2 = 1.2 V
11
V_DD < 4.5V
V_DD×0.75
—
MR high-level
input voltage
V_IH
V_DD ≥ 4.5V
V_DD×0.5
—
—
V
V_DD = 3.3 V
V_i1 = V _i2 = 1.2 V
—
V
V_DD = 5.0 V
V_i1 = V _i2 = 1.2 V
11
12
MR input
pull-down resistance
R_MR
0.5
2
—
MΩ ^{VDD = 5.5 V}
V_MR = 5.5 V
13
Notes: 1. When capacitor C_D is completely discharged and charging starts in the state that C_D pin voltage is 0 V, the
minimum value of delay time T_DLY0 is 7 ms. However, when the discharging time is short and charging starts
in the state that the voltage does not completely fall to 0 V, the minimum value of delay time T_DLY is 1.1 ms.
Then, the minimum value of Low time (reset time) of Vo2 is 1.1 ms as the delay time T_DLY. Refer to
Regulations for state of capacitor C_D electrical discharge and delay time on page 10 for details.
2. Refer to the characteristic curves on page 6 for temperature dependence of the main characteristics.
3. Refer to pages 8 and 9 for the test circuits.
R03DS0078EJ0200 Rev.2.00
Dec 19, 2015
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