R2J20651NP Datasheet, PDF (5/20 Pages) Renesas Technology Corp – Integrated Driver - MOS FET (DrMOS)

R2J20651NP
Pin Arrangement
10 9 8 7 6 5 4 3 2 1
VIN 11
VIN 12
VIN 13
VIN 14
VSWH 15
PGND 16
PGND 17
PGND 18
PGND 19
PGND 20
VIN
CGND
VSWH
40 PWM
39 DISBL#
38 THWN
37 CGND
36 GL
35 VSWH
34 VSWH
33 VSWH
32 VSWH
31 VSWH
21 22 23 24 25 26 27 28 29 30
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
LSDBL#
VCIN
VDRV
BOOT
CGND
GH
VIN
VSWH
PGND
GL
THWN
DISBL#
PWM
Pin No.
1
2
3
4
5, 37, Pad
6
8 to 14, Pad
7, 15, 29 to 35, Pad
16 to 28
36
38
39
40
Description
Low-side gate disable
Control input voltage (+5 V input)
Gate supply voltage (+5 V input)
Bootstrap voltage pin
Control signal ground
High-side gate signal
Input voltage
Phase output/Switch output
Power ground
Low-side gate signal
Thermal warning
Signal disable
PWM drive logic input
Remarks
When asserted "L" signal, Low-side gate disable
Driver Vcc input
5 V gate drive
To be supplied +5 V through internal SBD
Should be connected to PGND externally
Pin for Monitor
Pin for Monitor
Thermal warning when over 130°C
Disabled when DISBL# is "L"
Capable of both 3.3 V and 5 V logic input
REJ03G1743-0400 Rev.4.00 Mar 12, 2010
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