R2J20602NP_10 Datasheet, PDF (5/17 Pages) Renesas Technology Corp – Integrated Driver - MOS FET (DrMOS)

R2J20602NP
Pin Arrangement
14 13 12 11 10 9 8 7 6 5 4 3 2 1
VIN 15
VIN 16
VIN 17
VIN 18
VIN 19
VIN 20
VSWH 21
PGND 22
PGND 23
PGND 24
PGND 25
PGND 26
PGND 27
PGND 28
VIN
CGND
VSWH
56 PWM
55 DISBL#
54 Reg5V
53 NC
52 GL
51 CGND
50 VSWH
49 VSWH
48 VSWH
47 VSWH
46 VSWH
45 VSWH
44 VSWH
43 VSWH
29 30 31 32 33 34 35 36 37 38 39 40 41 42
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
CGND
NC
VLDRV
Pin No.
1, 6, 51, Tab
2, 53
3
VCIN
BOOT
GH
VIN
VSWH
PGND
GL
Reg5V
DISBL#
PWM
4
5
7
8 to 20, Tab
21, 40 to 50, Tab
22 to 39
52
54
55
56
Description
Control signal ground
No connect
Low side gate supply voltage
Control input voltage (+12 V input)
Bootstrap voltage pin
High side gate signal
Input voltage
Phase output/Switch output
Power ground
Low side gate signal
+5 V logic power supply output
Signal disable
PWM drive logic input
Remarks
Should be connected to PGND externally
For 5 V to 12 V gate drive voltage for Low side
gate driver
Driver Vcc input
To be supplied +5 V through internal SBD
Pin for Monitor
Pin for Monitor
Disabled when DISBL# is “L”
REJ03G1480-0500 Rev.5.00 Mar 12, 2010
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