PC4062_15 Datasheet, PDF (5/11 Pages) Renesas Technology Corp – J-FET INPUT LOW-POWER DUAL OPERATIONAL AMPLIFIER

µPC4062
ELECTRICAL CHARACTERISTICS (TA = 25°C, V^± = ±15 V)
Parameter
Input Offset Voltage
Input Offset Current ^{Note 7}
Input Bias Current ^{Note 7}
Large Signal Voltage Gain
Supply Current ^{Note 8}
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Symbol
VIO
IIO
IB
AV
ICC
CMR
SVR
Vom
Conditions
RS ≤ 50 Ω
RL ≥ 10 kΩ , VO = ±10 V
IO = 0 A
RL ≥ 10 kΩ
Common Model Input Voltage Range
VICM
Slew Rate
Unity Gain Frequency
Input Equivalent Noise Voltage Density
Channel Separation
Input Offset Voltage
Average VIO Temperature Drift
Input Offset Current ^{Note 7}
Input Bias Current ^{Note 7}
SR
AV = 1
funity
en
RS = 100 Ω, f = 1 kHz
VIO
∆VIO/∆T
IIO
IB
RS ≤ 50 Ω, TA = –20 to +70°C
TA = –20 to +70°C
TA = –20 to +70°C
TA = –20 to +70°C
MIN.
3000
70
70
±12
±12
TYP.
±2
±5
10
9000
400
90
90
+14.0
–13.6
+15
–13
3
1
30
120
±10
MAX.
Unit
±10
mV
±50
pA
100
pA
500
µA
dB
dB
V
V
V/µs
MHz
nV/√Hz
dB
±15
mV
µV/°C
±2
nA
3.5
nA
Notes 7. Input bias currents flow into IC. Because each currents are gate leak current of P-channel J-FET on input
stage. And that are temperature sensitive. Short time measuring method is recommendable to maintain the
junction temperature close to the operating ambient temperature.
8. This current flows irrespective of the existence of use.
Data Sheet G15108EJ3V0DS
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