M62392P_15 Datasheet, PDF (5/9 Pages) Renesas Technology Corp – 8-bit 12ch I2C BUS D/A Converter with Buffer Amplifiers

M62392P/FP
I²C BUS Format
STA
Slave address
Preliminary
WA
Sub address
A
DAC data
A STP
Digital Data Format
 Slave Address
First
Last
1
0
0
1
A2 A1 A0
 Sub Address
First
X
X
X
X
(Slave address)
 DAC Data
First
MSB
D7 D6 D5 D4
Chip select data
D3 D2 D1
Last
LSB
D0
Don't care
Last
S3
S2
S1
S0
Channel select data
(1) Chip Select Data
MSB
A2
0
0
0
:
1
Note:
LSB
A1
A0 CS2 CS1 CS0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
:
:
:
:
:
1
1
1
1
1
Lower 3 bits (A0, A1, A2) are a
programmable address. This IC is
accessed only when the lower 3 bits data
of slave address coincide with the data of
CS0 to CS2. (Refer to the upper table)
(2) Channel Select Data
MSB
LSB
S3 S2 S1 S0
Channel Selection
0
0
0
0 Don’t care
0
0
0
1 ch1 selection
0
0
1
0 ch2 selection
:
:
:
:
:
1
0
1
1 ch11 selection
1
1
0
0 ch12 selection
1
1
0
1 Don’t care
:
:
:
:
:
1
1
1
1 Don’t care
(3) DAC Data
First
Last
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
DAC Output
0
0
0
0
0
0
0
0
(VrefU − VrefL ) / 256 × 1 + VrefL
0
0
0
0
0
0
0
1
(VrefU − VrefL ) / 256 × 2 + VrefL
0
0
0
0
0
0
1
0
(VrefU − VrefL ) / 256 × 3 + VrefL
0
0
0
0
0
0
1
1
(VrefU − VrefL ) / 256 × 4 + VrefL
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
0
(VrefU − VrefL ) / 256 × 255 + VrefL
1
1
1
1
1
1
1
1
VrefU
R03DS0045EJ0400 Rev.4.00
Jun 03, 2011
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