M5M5T5636GP Datasheet, PDF (5/18 Pages) Renesas Technology Corp – MITSUBISHI LSIs 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM

MITSUBISHI LSIs
M5M5T5636GP –22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION
Pin
A0~A18
BWa#, BWb#,
BWc#, BWd#
CLK
E1#
Name
Synchronous
Address
Inputs
Synchronous
Byte Write
Enables
Clock Input
Synchronous
Chip Enable
Function
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins.
This signal registers the address, data, chip enables, byte write enables
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock's rising edge.
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
E2
Synchronous
Chip Enable
This active High input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
E3#
G#
ADV
CKE#
ZZ
W#
Synchronous
Chip Enable
Output Enable
Synchronous
Address
Advance/Load
Synchronous
Clock Enable
Snooze
Enable
Synchronous
Read/Write
This active Low input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW). This input can be used for memory depth expansion.
This active LOW asynchronous input enable the data I/O output drivers.
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
This active LOW input permits CLK to propagate throughout the device. When HIGH, the device
ignores the CLK input and effectively internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
This active HIGH asynchronous input causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When active, all other inputs are ignored. When this
pin is LOW or NC, the SRAM normally operates.
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
DQa,DQPa,DQb,DQPb Synchronous
DQc,DQPc,DQd,DQPd Data I/O
LBO#
VDD
VSS
VDDQ
VSSQ
MCH
NC
Burst Mode
Control
VDD
VSS
VDDQ
VSSQ
Must Connect High
No Connect
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins. Input data must meet setup and hold times around CLK rising edge.
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
Core Power Supply
Core Ground
I/O buffer Power supply
I/O buffer Ground
These pins should be connected to HIGH
These pins are not internally connected and may be connected to ground.
4/17
Preliminary
M5M5T5636GP REV.0.6