HD74LV2GT241A Datasheet, PDF (5/9 Pages) Renesas Technology Corp – Dual Bus Buffer Noninverted with 3-state Output / CMOS Logic Level Shifter

HD74LV2GT241A
Switching Characteristics
• V_CC = 3.3 ± 0.3 V
Item
Symbol
Propagation t_PLH
delay time t_PHL
Enable time t_ZH
t_ZL
Disable time t_HZ
t_LZ
T_a = 25°C
Min Typ
— 4.5
— 5.5
— 4.5
— 6.0
— 4.0
— 5.5
Max
9.0
11.5
9.0
11.5
10.0
13.5
T_a = –40 to 85°C
Test
FROM
Min Max ^{Unit Conditions (Input)}
1.0 10.5 ns C_L = 15 pF A
1.0 13.0
C_L = 50 pF
1.0 10.5 ns C_L = 15 pF OE
1.0 13.0
C_L = 50 pF ^{or OE}
1.0 11.5 ns C_L = 15 pF OE
1.0 15.0
C_L = 50 pF ^{or OE}
TO
(Output)
Y
Y
Y
• V_CC = 5.0 ± 0.5 V
Item
Symbol
Propagation t_PLH
delay time t_PHL
Enable time t_ZH
t_ZL
Disable time t_HZ
t_LZ
T_a = 25°C
Min Typ
— 3.4
— 4.3
— 3.4
— 4.4
— 3.2
— 4.0
Max
5.5
7.5
5.1
7.1
6.8
8.8
T_a = –40 to 85°C
Test
FROM
Min Max ^{Unit Conditions (Input)}
1.0 6.5 ns C_L = 15 pF A
1.0 8.5
C_L = 50 pF
1.0 6.0 ns C_L = 15 pF OE
1.0 8.0
C_L = 50 pF ^{or OE}
1.0 8.0 ns C_L = 15 pF OE
1.0 10.0
C_L = 50 pF ^{or OE}
TO
(Output)
Y
Y
Y
Operating Characteristics
• C_L = 50 pF
Item
Power dissipation
capacitance
Symbol
C_PD
T_a = 25°C
V_CC (V) _Min
Typ
5.0
—
11.5
Max ^Unit
—
pF
Test Conditions
f = 10 MHz
Rev.2.00, Oct.23.2003, page 5 of 8