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HD74LV2GT126A Datasheet, PDF (5/9 Pages) Renesas Technology Corp – Dual Bus Buffer with 3-state Output / CMOS Logic Level Shifter | |||
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HD74LV2GT126A
Switching Characteristics
⢠VCC = 3.3 ± 0.3 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
â 5.0
â 6.5
â 5.0
â 6.5
â 4.5
â 6.0
Max
9.0
11.5
9.0
11.5
10.0
13.5
Ta = â40 to 85°C
Test
FROM
Min Max Unit Conditions (Input)
1.0 10.5 ns CL = 15 pF A
1.0 13.0
CL = 50 pF
1.0 10.5 ns CL = 15 pF OE
1.0 13.0
CL = 50 pF
1.0 11.5 ns CL = 15 pF OE
1.0 15.0
CL = 50 pF
TO
(Output)
Y
Y
Y
⢠VCC = 5.0 ± 0.5 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
â 3.5
â 4.6
â 3.6
â 4.6
â 3.3
â 4.3
Max
5.5
7.5
5.1
7.1
6.8
8.8
Ta = â40 to 85°C
Test
FROM
Min Max Unit Conditions (Input)
1.0 6.5 ns CL = 15 pF A
1.0 8.5
CL = 50 pF
1.0 6.0 ns CL = 15 pF OE
1.0 8.0
CL = 50 pF
1.0 8.0 ns CL = 15 pF OE
1.0 10.0
CL = 50 pF
TO
(Output)
Y
Y
Y
Operating Characteristics
⢠CL = 50 pF
Item
Power dissipation
capacitance
Symbol
CPD
Ta = 25°C
VCC (V) Min
Typ
5.0
â
11.5
Max Unit
â
pF
Test Conditions
f = 10 MHz
Rev.2.00, Oct.23.2003, page 5 of 8
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