HD74LV273A Datasheet, PDF (5/10 Pages) Hitachi Semiconductor – Octal D-type Flip-Flops with Clear

HD74LV273A
Switching Characteristics
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
t_PHL
t_PLH/t_PHL
t_PHL
t_PLH/t_PHL
t_SU
t_h
t_W
Ta = 25°C
Min Typ
55 95
45 75
— 10.3
— 10.4
— 13.1
— 12.9
8.5 —
4.0 —
0.5 —
6.5 —
7.0 —
Max
—
—
19.0
18.3
22.8
22.1
—
—
—
—
—
Ta = –40 to 85°C
Min
Max
45
—
40
—
1.0
21.0
1.0
20.5
1.0
25.5
1.0
25.0
10.5
—
4.0
—
1.0
—
7.0
—
8.5
—
Unit
MHz
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
ns
ns
ns
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
t_PHL
t_PLH/t_PHL
t_PHL
t_PLH/t_PHL
t_SU
t_h
t_W
Ta = 25°C
Min Typ
75 140
50 110
— 6.9
— 7.1
— 8.7
— 9.1
5.5 —
2.5 —
1.0 —
5.0 —
5.5 —
Ta = –40 to 85°C
Max Min
Max
— 65
—
— 45
—
13.6 1.0
16.0
13.6 1.0
16.0
17.1 1.0
19.5
17.1 1.0
19.5
— 6.5
—
— 2.5
—
— 1.0
—
— 6.0
—
— 6.5
—
Unit
MHz
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
ns
ns
ns
Item
Maximum clock
frequency
Propagation
delay time
Setup time
Hold time
Pulse width
Symbol
fmax
t_PHL
t_PLH/t_PHL
t_PHL
t_PLH/t_PHL
t_SU
t_h
t_W
Ta = 25°C
Min Typ
120 205
80 160
— 4.7
— 4.8
— 6.0
— 6.2
4.5 —
2.0 —
1.0 —
5.0 —
5.0 —
Max
—
—
8.5
9.0
10.5
11.0
—
—
—
—
—
Ta = –40 to 85°C
Min
Max
100
—
70
—
1.0
10.0
1.0
10.5
1.0
12.0
1.0
12.5
4.5
—
2.0
—
1.0
—
5.0
—
5.0
—
Unit
MHz
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
ns
ns
ns
V_CC = 2.5 ± 0.2 V
FROM TO
(Input) (Output)
CLR
Q
CLK
Q
CLR
Q
CLK
Q
Data
CLR inactive
CLR L
CLK H or L
V_CC = 3.3 ± 0.3 V
FROM TO
(Input) (Output)
CLR
Q
CLK
Q
CLR
Q
CLK
Q
Data
CLR inactive
CLR L
CLK H or L
V_CC = 5.0 ± 0.5 V
FROM TO
(Input) (Output)
CLR
Q
CLK
Q
CLR
Q
CLK
Q
Data
CLR inactive
CLR L
CLK H or L
Rev.3.00 Jun. 25, 2004 page 5 of 9