HD151TS302RP_06 Datasheet, PDF (5/10 Pages) Renesas Technology Corp – Spread Spectrum Clock for EMI Solution

HD151TS302RP
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, C_L = 30 pF
Item
Cycle to cycle jitter ^{*1, 2}
Symbol
Min
t_CCS
—
Typ
| 250 |
Max
| 300 |
Unit
Test Conditions
Notes
SSCCLKOUT,
SSCOFF
24 MHz
SEL1:0 = 10
—
| 250 |
| 300 |
SSCCLKOUT,
Fig1
48 MHz
—
| 250 |
| 300 |
SSCCLKOUT,
SSC = –0.5%
24 MHz
SEL1:0 = 11
—
| 250 |
| 300 |
SSCCLKOUT,
48 MHz
Figure 1
—
| 250 |
| 300 |
SSCCLKOUT,
SSC = –3.0%
24 MHz
SEL1:0 = 01
—
| 250 |
| 300 |
SSCCLKOUT,
Figure 1
48 MHz
—
| 250 |
| 300 |
CLKOUT,
24 MHz &
Figure 1
Output frequency ^{*1, 2}
48 MHz
23.8
—
24.2
MHz SSCCLKOUT,
SSCOFF
XIN = 24 MHz
SEL1:0 = 10
47.3
—
48.7
SSCCLKOUT,
XIN = 48 MHz
23.7
—
24.2
SSCCLKOUT,
SSC = –0.5%
XIN = 24 MHz
SEL1:0 = 11
47.0
—
48.7
SSCCLKOUT,
XIN = 48 MHz
23.1
—
24.2
SSCCLKOUT,
SSC = –3.0%
XIN = 24 MHz
SEL1:0 = 01
45.9
—
48.7
SSCCLKOUT,
XIN = 48 MHz
23.8
—
24.2
CLKOUT,
24 MHz
47.3
—
48.7
CLKOUT,
Slew rate ^*1
Clock duty cycle ^*1
Output impedance ^*1
48 MHz
t_SL
1.0
—
—
V/ns @48 MHz CLKOUT 0.4 V to 2.4 V
45
50
55
%
—
30
—
Ω
Spread spectrum
modulation frequency ^*1
—
33
—
KHz @48 MHz
SSCCLKOUT
Input clock frequency
Stabilization time ^*1,3
10
—
60
MHz
—
—
2
ms
Notes: 1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after power up.
SSCCLKOUT
(or CLKOUT)
tcycle n
tcycle n+1
t _CCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.6.00 Apr 07, 2006 page 5 of 9