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2SJ555 Datasheet, PDF (5/8 Pages) Hitachi Semiconductor – Silicon P Channel MOS FET High Speed Power Switching | |||
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2SJ555
â100
Reverse Drain Current vs.
Source to Drain Voltage
â80
â60
â10 V
â40
â5 V
â20
VGS = 0
Pulse Test
0
0 â0.4 â0.8 â1.2 â1.6 â2.0
Source to Drain Voltage VSD (V)
Maximum Avalanche Energy vs.
Channel Temperature Derating
500
IAP = â60 A
VDD = â25 V
400
duty < 0.1 %
Rg ⥠50 â¦
300
200
100
0
25 50
75 100 125 150
Channel Temperature Tch (°C)
Normalized Transient Thermal Impedance vs. Pulse Width
3
D=1
1
0.5
Tc = 25°C
0.3
0.2
0.1
0.1
0.05
0.02
0.03
0.01
1shot
pulse
0.01
10 µ
100 µ
θch â c (t) = γ s (t) ⢠θch â c
θch â c = 1.0°C/W, Tc = 25°C
PDM
D = PW
T
PW
T
1m
10 m
100 m
1
10
Pulse Width PW (S)
Vin
â15 V
Avalanche Test Circuit
VDS
Monitor
Rg
50 â¦
L
IAP
Monitor
D.U.T
VDD
Avalanche Waveform
EAR =
1
2
⢠L ⢠IAP2 â¢
VDSS
VDSS â VDD
IAP
ID
V(BR)DSS
VDS
VDD
0
Rev.3.00 Sep 07, 2005 page 5 of 7
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