H8S15 Datasheet, PDF (483/904 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

H8S/2215 Group
Section 13 Serial Communication Interface
Figure 13.11 shows a sample flowchart for transmission in asynchronous mode.
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
All data transmitted?
Yes
Read TEND flag in SSR
TEND = 1
Yes
Break output?
Yes
Clear DR to 0 and set DDR to 1
No
[3]
No
No
[4]
[1] SCI initialization:
The TxD pin is automatically designated
as the transmit data output pin.
After the TE bit is set to 1, a frame of 1s
is output, and transmission is enabled.
[2] SCI status check and transmit data write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, read 1
from the TDRE flag to confirm that writing
is possible, then write data to TDR, and
then clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC or the DTC*
is activated by a transmit data empty
interrupt (TXI) request, and data is written
to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial transmission,
set DDR for the port corresponding to the
TxD pin to 1, clear DR to 0, then clear the
TE bit in SCR to 0.
Clear TE bit in SCR to 0
<End>
Note: * Checking and clearing of the TDRE flag are performed automatically by the DTC when the DTC’s DISEL bit is
cleared to 0 and the transfer counter value is not 0. Consequently, it is necessary to use the CPU to clear the
TDRE flag if DISEL is set to 1 or if the transfer counter value is 0.
Figure 13.11 Sample Serial Transmission Data Flowchart
REJ09B0140-0900 Rev. 9.00
Sep 16, 2010
Page 429 of 846