H838537 Datasheet, PDF (463/508 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series

Appendix
A.3 Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × S_I + J × S_J + K × S_K + L × S_L + M × S_M + N × S_N
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S_I = 2, S_L = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
S_I = S_J = S_K = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 1.00 May 30, 2008 Page 443 of 484
REJ09B0436-0100