M37753M8C-XXXFP Datasheet, PDF (46/110 Pages) Renesas Technology Corp – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M37753M8C-XXXFP, M37753M8C-XXXHP
M37753S4CFP, M37753S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SERIAL I/O PORTS
Two independent serial I/O ports are provided. Figure 54 shows a
block diagram of the serial I/O ports.
Bits 0, 1, and 2 of the UARTi(i = 0,1) Transmit/Receive mode register
shown in Figure 55 are used to determine whether to use port P8 as
parallel port, clock synchronous serial I/O port, or asynchronous
(UART) serial I/O port using start and stop bits.
Figures 56 and 57 show the connections of receiver/transmitter ac-
cording to the mode.
Figure 58 shows the bit configuration of the UARTi Transmit/Receive
control register.
Each communication method is described below.
Data bus(odd)
Data bus(even)
Bit converter
RXDi
Clock source selection
Pf2
Pf16
Pf64
Pf512
CLKi
External
CTSi/RTSi
Bit rate
generator
UART0(3116)
UART1(3916)
Internal
1/(n + 1)
Divider
0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Receive buffer register
UART0(3716,3616)
UART1(3F16,3E16)
UART receive
1/16 Divider
Receive
control
Clock synchronous
circuit
Receive register
Receive clock
UART transmission
1/16 Divider
Transmission
Clock synchronous
control circuit
Clock synchronous
(Internal clock)
1/2 Divider
Transmission clock
Transmit register
TXDi
Clock synchronous
Clock synchronous
(Internal clock)
(External clock)
D8
D7 D6 D5 D4 D3 D2 D1 D0
Transmit
buffer register
UART0(3316,3216)
Data bus
UART1(3B16,3A16)
(odd) _{Bit converter}
Fig. 54 Serial I/O port block diagram
76543210
Addresses
UART 0 Transmit/Receive mode register 3016
UART 1 Transmit/Receive mode register 3816
Serial I/O mode select bit
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal/External clock select bit
0 : Internal clock
1 : External clock
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
Even/Odd parity select bit
0 : Odd parity
1 : Even parity
Parity enable select bit
0 : No parity
1 : With parity
Sleep select bit
0 : No sleep
1 : Sleep
Fig. 55 UARTi Transmit/Receive mode register bit configuration
Data bus(even)
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