H83318 Datasheet, PDF (420/574 Pages) Renesas Technology Corp – Single-Chip Microcomputer

Section 18 Power-Down State
18.1 Overview
The H8/3318 has a power-down state that greatly reduces power consumption by stopping some or
all of the chip functions. The power-down state includes three modes:
1. Sleep mode—a software-triggered mode in which the CPU halts but the rest of the chip
remains active
2. Software standby mode—a software-triggered mode in which the entire chip is inactive
3. Hardware standby mode—a hardware-triggered mode in which the entire chip is inactive
Table 18.1 lists the conditions for entering and leaving the power-down modes. It also indicates
the status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 18.1 Power-Down State
Mode
Entering
CPU Sup.
Procedure Clock CPU DTU Reg’s. Mod.
Exiting
RAM I/O Ports Methods
Sleep
mode
Execute Run Halt Run Held Run
SLEEP
instruction
Held Held
• Interrupt
• RES
• STBY
Software
standby
mode
Set SSBY Halt
bit in
SYSCR to
1, then
execute
SLEEP
instruction
Halt Halt Held
Halt and Held Held
initialized
• NMI
• IRQ₀–IRQ₂,
IRQ₆
• RES
• STBY
Hardware Set STBY Halt
standby pin to low
mode
level
Halt Halt Not
held
Halt and Held High
• STBY and
initialized
impedance _RES
state
Legend
SYSCR: System control register
SSBY: Software standby bit
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