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M37273MFH Datasheet, PDF (41/130 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER | |||
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MITSUBISHI MICROCOMPUTERS
M37273MFHâXXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
S Slave address R/W A Data A Data A/A P
7 bits
â0â
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
â1â
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Data
A Data A/A P
7 bits
â0â
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Sr
Slave address
1st 7 bits
R/W
Data
A Data
A
P
7 bits
â0â
8 bits
7 bits
â1â 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
From master to slave
From slave to master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master
I2C-BUS interface
(1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB,
CLB etc. is executed for each register of the multi-master I2C-BUS
interface are described below.
â¢I2C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become a value not intended.
â¢I2C address register (S0D)
When the read-modify-write instruction is executed for this register
at detecting the STOP condition, data may become a value not
______
intended. It is because hardware changes the read/write bit (RBW)
at the above timing.
â¢I2C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
â¢I2C control register (S1D)
When the read-modify-write instruction is executed for this register
at detecting the START condition or at completing the byte transfer,
data may become a value not intended. Because hardware changes
the bit counter (BC0âBC2) at the above timing.
â¢I2C clock control register (S2)
The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure us-
ing multi-master
âProcedure example (The necessary conditions of the generating
procedure are described as the following â to â).
â¢
â¢
LDA â
SEI
BBS 5,S1,BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
â¢
â¢
BUSBUSY:
CLI
â¢
â¢
(Taking out of slave address value)
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
(Interrupt enabled)
âUse âSTA,â âSTXâ or âSTYâ of the zero page addressing instruction
for writing the slave address value to the I2C data shift register.
âUse âLDMâ instruction for setting trigger of START condition gener-
ating.
âWrite the slave address value of above â and set trigger of START
condition generating of above â continuously shown the above
procedure example.
âDisable interrupts during the following three process steps:
⢠BB flag confirming
⢠Writing of slave address value
⢠Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
Rev. 1.0
40
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