RJK1053DPB_13 Datasheet, PDF (4/7 Pages) Renesas Technology Corp – 100V, 25A, 13m max Silicon N Channel Power MOS FET Power Switching

RJK1053DPB
Static Drain to Source on State Resistance
vs. Temperature
40
Pulse Test
I_D = 12.5 A
32
24
16
V_GS = 4.5 V
10 V
8
0
–25 0 25 50 75 100 125 150
Case Temperature Tc (°C)
Dynamic Input Characteristics
200
20
I_D = 25 A
160
16
120
80
V_DS
40
0
0
20
V_DD = 50 V
25 V
10 V
V_{GS 12}
8
V_DD = 50 V
4
25 V
10 V
0
40 60 80 100
Gate Charge Qg (nC)
Maximum Avalanche Energy vs.
Channel Temperature Derating
20
I_AP = 12.5 A
V_DD = 50 V
16
duty < 0.1 %
Rg ≥ 50 Ω
12
8
4
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Preliminary
10000
Typical Capacitance vs.
Drain to Source Voltage
Ciss
1000
100
Coss
Crss
V_GS = 0 V
f = 1 MHz
10
0
10 20 30 40 50
Drain to Source Voltage V_DS (V)
Reverse Drain Current vs.
Source to Drain Voltage
50
5V
40
10 V
Pulse Test
30
20
10
V_GS = 0 V
0
0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage V_SD (V)
R07DS0084EJ0200 Rev.2.00
Apr 11, 2013
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