RJK03E2DNS Datasheet, PDF (4/7 Pages) Renesas Technology Corp – Silicon N Channel Power MOS FET Power Switching

RJK03E2DNS
Static Drain to Source on State Resistance
vs. Temperature
40
Pulse Test
32
24
I_D = 2 A, 5 A, 10 A
16
V_GS = 4.5 V
8
10 V
2 A, 5 A, 10 A
0
–25 0 25 50 75 100 125 150
Case Temperature Tc (°C)
Dynamic Input Characteristics
50
20
I_D = 16 A
40
30 _VDS
20
V_DD = 25 V
10 V
16
V_GS
12
8
10
V_DD = 25 V
4
10 V
0
0
0
5
10 15 20 25
Gate Charge Qg (nc)
Maximum Avalanche Energy vs.
Channel Temperature Derating
10
8
6
4
2
0
25 50 75 100 125 150
Channel Temperature Tch (°C)
Preliminary
10000
Typical Capacitance vs.
Drain to Source Voltage
3000
Ciss
1000
300
100
30 _{V0GS = 0}
f = 1 MHz
10
10
Coss
Crss
20
30
Drain to Source Voltage V_DS (V)
Reverse Drain Current vs.
Source to Drain Voltage
20
10 V
5V
16
Pulse Test
12
8
4
V_GS = 0, –5 V
0
0.4 0.8 1.2 1.6 2.0
Source to Drain Voltage V_SD (V)
REJ03G1904-0200 Rev.2.00
Apr 06, 2010
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