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R1EX24512BSAS0G_15 Datasheet, PDF (4/18 Pages) Renesas Technology Corp – Two-wire serial interface 512k EEPROM (64-kword 꼌 8-bit) | |||
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R1EX24512BSAS0G/R1EX24512BTAS0G
AC Characteristics
Test Conditions
ï· Input pules levels:
ï¾ VIL = 0.2 ï´ VCC
ï¾ VIH = 0.8 ï´ VCC
ï· Input rise and fall time: ï£ 20 ns
ï· Input and output timing reference levels: 0.5 ï´ VCC
ï· Output load: TTL Gate + 100 pF
(Ta = ï40 to +105ï°C, VCC = 1.8 to 5.5 V)
Parameter
Symbol
VCC = 1.8 V to 5.5 V
Min
Typ
Max
VCC = 2.5 V to 5.5 V
Min
Typ Max Unit
Notes
Clock frequency
fSCL
ï¾
ï¾
400
ï¾
ï¾ 1000 kHz
Clock pulse width low
tLOW
1200
ï¾
ï¾
600
ï¾
ï¾
ns
Clock pulse width high
tHIGH
600
ï¾
ï¾
400
ï¾
ï¾
ns
Noise suppression time
tI
ï¾
ï¾
50
ï¾
ï¾
50
ns
1
Access time
tAA
100
ï¾
900
100
ï¾
550
ns
Bus free time for next mode tBUF
1200
ï¾
ï¾
500
ï¾
ï¾
ns
Start hold time
tHD.STA
600
ï¾
ï¾
250
ï¾
ï¾
ns
Start setup time
tSU.STA
600
ï¾
ï¾
250
ï¾
ï¾
ns
Data in hold time
tHD.DAT
0
ï¾
ï¾
0
ï¾
ï¾
ns
Data in setup time
tSU.DAT
100
ï¾
ï¾
100
ï¾
ï¾
ns
Input rise time
tR
ï¾
ï¾
300
ï¾
ï¾
300
ns
1
Input fall time
tF
ï¾
ï¾
300
ï¾
ï¾
100
ns
1
Stop setup time
tSU.STO
600
ï¾
ï¾
250
ï¾
ï¾
ns
Data out hold time
tDH
50
ï¾
ï¾
50
ï¾
ï¾
ns
Write protect hold time
tHD.WP
1200
ï¾
ï¾
600
ï¾
ï¾
ns
Write protect setup time
tSU.WP
0
ï¾
ï¾
0
ï¾
ï¾
ns
Write cycle time
tWC
ï¾
ï¾
5
ï¾
ï¾
5
ms
2
Notes: 1. Not 100ï¥ tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
R10DS0111EJ0200 Rev.2.00
Feb. 18, 2013
Page 4 of 16
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