NP110N04PDG_15 Datasheet, PDF (4/10 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

NP110N04PDG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage ^Note
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 μA
VDS = 10 V, ID = 55 A
VGS = 10 V, ID = 55 A
VGS = 4.5 V, ID = 55 A
Input Capacitance
Ciss
VDS = 25 V
Output Capacitance
Coss
VGS = 0 V
Reverse Transfer Capacitance
Turn-on Delay Time
Crss
td(on)
f = 1 MHz
VDD = 20 V, ID = 55 A
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
tr
td(off)
tf
QG
VGS = 10 V
RG = 0 Ω
VDD = 32 V
Gate to Source Charge
QGS
VGS = 10 V
Gate to Drain Charge
Body Diode Forward Voltage ^Note
QGD
VF(S-D)
ID = 110 A
IF = 110 A, VGS = 0 V
Reverse Recovery Time
Reverse Recovery Charge
Note Pulsed
trr
IF = 110 A, VGS = 0 V
Qrr
di/dt = 100 A/μs
MIN. TYP. MAX. UNIT
1
μA
±100 nA
1.5 2.0 2.5 V
45 89
S
1.4 1.8 mΩ
2.1 3.2 mΩ
14500 25700 pF
1360 2130 pF
810 1610 pF
46 120 ns
124 350 ns
122 260 ns
19 60 ns
230 390 nC
42
nC
75
nC
0.9 1.5 V
55
ns
72
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D17561EJ2V0DS