M64897GP Datasheet, PDF (4/14 Pages) Mitsubishi Electric Semiconductor – PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC

M64897GP
Pin Description
Pin
No. Symbol
Pin name
1 fin
Prescaler input
2 GND
GND
3 V_CC1
Power supply voltage 1
4 V_CC2
Power supply voltage 2
5 BS4
Band switching outputs
6 BS3
7 BS2
8 BS1
9 VDC
DC/DC power supply voltage
10 Ipk
Peak current detect
11 SWE
12 +B
13 Vtu
14 Vin
Switching output
Power supply voltage
Tuning output
Filter input (Charge pump output)
15 LD/ftest Lock detect/Test port
16 ADC
17 SCL
18 SDA
AD converter input
Clock input
Data input
19 ADS
20 Xin
Address switching input
This is connected to the crystal
oscillator
Function
Input for the VCO frequency.
Ground to 0 V.
Power supply voltage terminal.5.0 V ± 0.5 V
Power supply for band switching, V_CC1 to 10 V
PNP open collector method is used.
When the band switching data is “H”, the output is ON.
When it is “L”, the output is OFF.
DC/DC power supply voltage terminal.5.0 V ± 0.5 V
When potential difference with VDC terminal becomes
more than 0.33 V by current limiting detector of DC/DC
converter, the listing rises with off.
DC/DC converter oscillator output.
Power supply voltage for tuning voltage.
This supplies the tuning voltage.
This is the output terminal for the LPF input and charge
pump output. When the phase of the programmable divider
output (f 1/N) is ahead compared to the reference
frequency (f_REF), the “source” current state becomes active.
If it is behind, the “sink” current becomes active.
If the phases are the same, the high impedance state
becomes active.
Lock detector output. When loop of phase locked loop
locked it, it rises with “H” level in “L” level or unlock.
In control byte data input, the programmable freq. divider
output and reference freq. output is selected by the test
mode.
A/D conversion of the input voltage.
Data is read into the shift register when the clock signal
falls..
Input for band SW and programmable freq. divider set up.
In lead mode, it outputs lock detector output and power
down flag and a state of 5 level A/D converter.
Chip address sets it up with the input condition of terminal.
4.0 MHz crystal oscillator is connected.
Rev.2.00 Jun 14, 2006 page 4 of 13