HD74LV1GT125A Datasheet, PDF (4/8 Pages) Renesas Technology Corp – Bus Buffer Gate with 3.state Output / CMOS Logic Level Shifter

HD74LV1GT125A
Electrical Characteristic
• Ta = –40 to 85°C
Item
Symbol V_CC (V) *
Min
Typ
Max
Unit
Test condition
Input voltage
3.0 to 3.6
1.5
—
—
V_IH
4.5 to 5.5
2.0
—
—
V
3.0 to 3.6
—
—
0.6
V_IL
4.5 to 5.5
—
—
0.8
Hysteresis voltage
3.3
V_H
5.0
—
0.10
—
—
0.15
—
V
V_T+ – V_T–
Min to Max V_CC–0.1
—
—
I_OH = –50 µA
V_OH
3.0
2.48
—
—
I_OH = –6 mA
Output voltage
4.5
3.8
—
—
V
I_OH = –12 mA
Min to Max —
—
0.1
I_OL = 50 µA
V_OL
3.0
—
—
0.44
I_OL = 6 mA
4.5
—
—
0.55
I_OL = 12 mA
Input current
I_IN
0 to 5.5
—
—
±1
µA V_IN = 5.5 V or GND
Off state output
current
I_OZ Min to Max
—
—
±5
µA V_O = 5.5 V or GND
Quiescent
supply current
I_CC
5.5
∆I_CC
5.5
—
—
10
µA
V_IN = V_CC or GND,
I_O = 0
—
—
1.5
mA ^{One input VIN = 3.4 V,}
other input V_CC or GND
Output leakage current I_OFF
0
—
—
5
µA V_IN or V_O = 0 to 5.5 V
Input capacitance
C_IN
5.0
—
3.0
—
pF V_IN = V_CC or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
• V_CC = 3.3 ± 0.3 V
Item
Symbol
Propagation
t_PLH
delay time
t_PHL
Enable time
t_ZH
t_ZL
Disable time
t_HZ
t_LZ
Ta = 25°C
Min Typ Max
—
4.5
9.0
—
6.0 11.5
—
4.5
9.0
—
6.0 11.5
—
4.0 10.0
—
5.5 13.5
• V_CC = 5.0 ± 0.5 V
Item
Symbol
Propagation
t_PLH
delay time
t_PHL
Enable time
t_ZH
t_ZL
Disable time
t_HZ
t_LZ
Ta = 25°C
Min Typ Max
—
3.4
5.5
—
4.3
7.5
—
3.4
5.1
—
4.4
7.1
—
3.2
6.8
—
4.0
8.8
Ta = –40 to 85°C
Min
Max
1.0
10.5
1.0
13.0
1.0
10.5
1.0
13.0
1.0
11.5
1.0
15.0
Ta = –40 to 85°C
Min
Max
1.0
6.5
1.0
8.5
1.0
6.0
1.0
8.0
1.0
8.0
1.0
10.0
Unit
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
FROM TO
(Input) (Output)
A
Y
OE
Y
OE
Y
Unit
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
FROM TO
(Input) (Output)
A
Y
OE
Y
OE
Y
REJ03D0123-0900 Rev.9.00, Mar 21, 2008
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