HD74LS375 Datasheet, PDF (4/6 Pages) Hitachi Semiconductor – Quadruple Bistable Latches

HD74LS375
Testing Method
Test Circuit
DG
V_CC Q _Q
P.G.
Zout = 50Ω
P.G.
Zout = 50Ω
DQ
GQ
CL
RL
RL
CL
Notes:
1. Test is put into the each latch.
2. C_L includes prove and jig capacitance.
3. All diodes are 1S2074(H).
Waveform
Notes:
t_TLH
1µs
t_THL
1µs
90%
90%
3V
D
1.3 V
1.3 V
1.3 V
10%
10%
t_su
t_TLH
t_h
t_THL
t_su
t_h
0V
90% 90%
3V
G
1.3 V 1.3 V
1.3 V 1.3 V
10% 10%
0V
500ns
t_PLH
t_PLH
500ns
t_PHL
t_PHL
Q
V_OH
1.3 V
1.3 V
t_PLH
V_OL
Q
1.3 V
t_PHL
t_PHL
t_PLH
1.3 V
V_OH
V_OL
1. Input pulse; D input: PRR = 500 kHz, G input: PRR = 1 MHz, t_THL ≤ 10 ns, t_TLH ≤ 10 ns.
2. When measuring propagation delay times from the D input, the corresponding G input must be
held high.
Rev.2.00, Feb.18.2005, page 4 of 5